pmc-931138 (r6) ? 1998 pmc-sierra, inc. october, 1998 PM7375 pmc-sierra,inc. atm sar and phy processor for pci bus lasar-155 features ? combines phy, atm, aal5, and pci dma controller on a single device to simplify the design, programming, and manufacturing of atm adapters. conforms to atm forum user- network interface (uni) specification version 3.1, bellcore standard ta- nwt-001113, and itu-t recommendations i.432 and i.363. host interface provides a 32-bit, 33 mhz peripheral component interconnect (pci) local bus specifications version 2.1 interface and supports both bus- master and bus-slave access modes. other 32-bit system buses can be accommodated using external glue logic. implements an efficient dma controller to manage the transfer of packets between the sar engine and the host memory with minimum pci host intervention. there is no need for a local packet memory. the transmit and receive dma channels support scatter/gather capabilities where a packet can be stored in non-contiguous buffers. provides an 8-cell fifo in the transmit direction and a 96-cell fifo in the receive direction to allow for up to 270 s of pci bus latency in the receive direction. physical layer incorporates the industry standard pmc pm5346 s/uni ? -lite to provide sonet and sdh interfaces at sts- 3c/stm-1 (155.52 mb/s) and sts-1 (51.84 mb/s) rates. provides on-chip clock recovery and clock synthesis units that are compliant with bellcore tr-nwt-000253 issue 2 and itu-t recommendation g.958 jitter requirements. performs sonet/sdh framer, overhead, and cell processing functions at sts-3c/stm-1 and sts-1 rates. atm and adaptation layers supports the simultaneous segmentation and reassembly of 128 open virtual circuits (vcs) in both transmit and receive directions. provides leaky bucket peak cell rate (pcr) enforcement using eight programmable peak queues coupled with sub-rate control on a per-vc basis. implements sustainable cell rate (scr) enforcement using a token generation mechanism on a per-vc basis. provides an internal vc parameter storage for both the 128 transmit and 128 receive vcs to simplify the design of the atm adapter and to sustain a high data throughput rate. multipurpose port in bypass mode, provides an 8-bit sci-phy ? or utopia-compliant port to connect to an external physical layer processor such as pm7345 s/uni- pdh ? for ds3/e3 uni. in non-bypass mode, supports the insertion and extraction of constant bit rate (cbr) cells that carry encoded video and audio signals. microprocessor interface in slave mode, provides a generic 8-bit microprocessor port for the configuration, control, and monitoring by an optional microprocessor. in master mode, allows for the control of two external devices without glue logic. packaging provides a standard 5-signal p1149.1 jtag test port for boundary scan board test purposes. implemented in low power, 0.6 micron, +5 v cmos technology with ttl and pseudo ecl (pecl) compatible inputs and outputs. packaged in 208-pin plastic quad flat pack (pqfp) package. applications atm workstations and adapters atm bridges, switches, and hubs multimedia terminals block diagram d[15:0] a[8:0] ale csb wrb rdb rstb microprocessor interface intb pciintb pciclk perrb serrb reqb gntb receive atm cell processor receive framer and overhead processor tcp/tldclk tgfc/tld xoff tclk tfpo rcp/rldclk rgfc/rld rfp rclk ralm receive line interface rrclk- alos+ alos- rrclk+ rxd- rxd+ txc txd- txd+ receive atm and adaptation processor sar perfor- mance monitor connection parameter store transmit atm traffic shaper trclk- trclk+ jtag port transmit framer and overhead processor transmit atm cell processor transmit line interface transmit atm and adaptation processor rxphybp rrdenb rsoc rdat[7:0] rfifoeb/ rfifofb trstb tms tck tdi tdo mpenb lf+, lf-, lfo romp tdat[7:0] tsoc twrenb txphybp tfifofb/tfifoeb devselb idsel irdby stopb frameb trdyb lockb pci dma controller par ad[31:0] c/beb[3:0] pciclko sysclk
head office: pmc-sierra, inc. #105 - 8555 baxter place burnaby, b.c. v5a 4v7 canada tel: 604.415.6000 fax: 604.415.6200 PM7375 lasar-155 atm sar and phy processor for pci bus to order documentation, send email to: document@pmc-sierra.com or contact the head office, attn: document coordinator all product documentation is available on our web site at: http://www.pmc-sierra.com for corporate information, send email to: info@pmc-sierra.com pmc-931138 (r6) ? 1998 pmc-sierra, inc. october, 1998 saturn, sci-phy, and s/uni are trademarks of pmc-sierra, inc. typical applications atm adapter for pci bus interface to external physical layer processor (s/uni-pdh) PM7375 lasar-155 lasar-155 atm sar and phy processor for pci bus optional microprocessor ad[31:0] pci bus e/o o/e txd+/- rxd+/- line driver and transformer a[15:0] d[7:0] controls transformer, equalizer, and line receiver controls fiber facility utp-5 facility or optional eprom pci bus ds3/e3 liu pm7345 s/uni ? -pdh saturn ? user net- work interface for pdh applications 75 ? coax fwdata[7:0] frdata[7:0] controls controls a[7:0] d[7:0] PM7375 lasar-155 lasar-155 atm sar and phy processor for pci bus ad[31:0] tdat[7:0] controls rdat[7:0] controls controls a[15:0] d[7:0]
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